The present invention relates to storage systems equipped with disk drives, and more particularly to methods of controlling cache memory of those storage systems.
Conventionally, in order to speed up an I/O operation of data to and from a host system (host computer), a storage system equipped with disk drives, in particular, a disk array system equipped with a plurality of disk drives includes a cache memory composed of far faster semiconductor memories than the disk drives themselves. Through the use of the cache memory, the storage system has operated to temporarily store data to be read from or written in the host computer. For example, this type of technology is disclosed in JP-A-11-203201.
In such a technology as disclosed in JP-A-11-203201, for the purpose of facilitating control of the cache memory and sharing the cache memory among a plurality of host computers, the data to be stored in the cache memory, in particular, the data written by the host computer is managed and controlled in a manner to correspond with the disk drive. That is, as to the data stored in the cache memory, which the disk drive is and where the location on the disk drive thereof to or from which the data is written or read is are registered. If a plurality of host computers read or write the data on the same disk drive, those host computers are arranged to share the same cache memory and use the same area on the cache memory.
Further, as the prior art, JP-A-2003-345520 discloses an example of a storage system arranged to control the cache memory in a manner to correspond with the host computer and locate the sharing network between the cache memory and the disk drive. This technology of JP-A-2003-345520 is arranged to make access to the cache memory without having to convert a virtual volume into a physical disk drive, and no passage time of the data through the sharing network being needed, which makes it possible to speed up the operation of the storage system as viewed from the host computer.
Further, the prior art of the hierarchical storage system is disclosed in JP-A-10-063576 or JP-A-07-200187.
However, in such a system as disclosed in JP-A-11-203201, for the data, in particular, the write data, all cache memories located in the storage system are required to be physically shared from all host computers to be connected with the storage system. Hence, the system should have some kind of sharing network connecting between the host interfaces to be connected with the host computer and the cache memories. This thus requires a passage time of the data through the sharing network in transferring the data with the cache memory as viewed from the host computer, which leads to a limitation of speeding up the operation of the storage system.
Further, the conventional system has been often arranged as follows. A disk drive is virtualized to the host computer so that the virtual volume may be viewed from the host computer. Then, in the storage system, this virtual volume is translated into the physical disk drive. In this system, in order to make access to the cache memory, it is necessary to translate the virtual volume into the physical disk drive and then make access to the corresponding cache memory to the disk drive. This requires an additional translation time and makes the faster operation impractical.
Moreover, in the technology disclosed in JP-A-2003-345520, if the cache memory may be connected with lots of host computers, the cache memories are not shared among the different host computers, so that the cache memory may be provided for each host computer individually. This needs a great deal of cache memories. Further, for duplicating the data written by the host computer in the cache memory for the purpose of improving reliability, a further double capacity of cache memories, or a rather sophisticated control such as a sharing of the cache memory by about two host computers is required.
In the technology disclosed in JP-A-10-063576 or JP-A-07-200187, the upper cache memory to be connected with the host computer is unique for the purpose of simplifying the coherence control of the upper cache memory and the lower cache memory. If, therefore, lots of host computers are tried to be connected with the cache memory, the capacity of the upper cache memory is required to be gigantic. This leads to difficulty in reducing the cost and improving the performance.